The core business of SSMC as a CMOS silicon foundry is wafer fabrication and providing exclusive foundry manufacturing services to our partners - NXP and TSMC.

Our belief in quality in all aspects of our business has translated to dedicated employees working together to offer to customers the highest quality CMOS wafer fabrication.

We offer 0.25-micron - 0.14-micron with derivatives and embedded flash CMOS manufacturing process. Key device features include dual gate oxide, low leakage, high speed, low power, mixed mode and embedded flash. Various options are available for each of these nodes, for example polyimide coating for stress relief, thick top metal for power management and inductors, redistribution layer for bumping packaging process and high resistivity substrate for noise suppression and RF applications.


SSMC offers advanced wafer fabrication capabilities ranging from 0.11 micron to 0.14 micron technology nodes. Our wide portfolio of silicon proven derivatives and options are capable of handling diverse characteristics and requirements by today's customers.

To name a few, these include Embedded Flash, Automotive grade, Dual Gate Oxide, Low Leakage, High Speed, Low Power & Mixed Mode capabilities. With the wide variety of options, our customers can confidently take advantage of our manufacturing expertise using these advanced processes to achieve Time-To-Market & Time-To-Volume successes.


In line with the preparation for our future manufacturing needs, we will be expanding our production capacity to 68,000 wafers per month by 2017.


A key indicator of the performance of the fab is the line yield and defect density. We are committed to best-in-class yield performance by constantly benchmarking against the highest standards set by our motherfabs and the leaders in the foundry industry.

With a fab line yield of consistently 98-99 per cent and world-class levels of electrical wafer sort yield, we strive to meet our customers’ production needs for volume market delivery and the highest possible quality wafers.

Extending the close co-operation with the customers in the prototyping phase, our engineering team prepares the product for volume production. Corner lots or matrix lots are normally processed to determine the process fit and margins between the design and process. Yield roadmaps and yield improvement activities are systematically planned together with the customers to effectively bring the customer product to mass production. Such close cooperation and mutual learning help ensure that world-class yield levels are achieved quickly.

As an integral part of our yield improvement efforts, we are constantly monitoring and studying all possible methods to reduce the defect density for the wafer manufacturing processes. One approach is to implement best-known-methods from our motherfabs. Another is the continuous monitoring and feedback of defect levels from all fab processing tools.

To support yield and baseline defect density improvements, we are equipped with a full-scale Failure Analysis lab and an experienced team that provide extensive and advanced Failure Analysis services.

The chart below gives a brief overview of the whole process undertaken to ensure best-in-class D0 performances.